myvtm/DevAdapter/cw/cardissuer.1.1/sankyoDef.h

// sankyoDef.h:
//
//////////////////////////////////////////////////////////////////////

#if !defined(SANKYODEF)
#define SANKYODEF

#if _MSC_VER > 1000
#pragma once
#endif // _MSC_VER > 1000

/*   be aware of alignment   */
#pragma pack(push,1)


#define PWR_OFF_TO_INSIDE   1
#define PWR_OFF_TO_FRONT    2
#define PWR_OFF_TO_REAR     3

#define RESET_TO_FRONT              0x34
#define RESET_TO_REAR                 0x35
#define RESET_TO_HOLD                0x36
#define RESET_NO_MOVEMENT     0x37

struct SANKYO_CMD
{
    unsigned char idn;
    unsigned char command[2];
    unsigned int parameterLen;
    unsigned char parameter[2056];
};

struct SANKYO_RSP
{
    unsigned char jdgPart;  // 'IDN'
    unsigned char rcm[2];   // 'CMD'(cm+pm)
    unsigned char res[2];   // status(error) code part
    unsigned char res_ext;  // extend status part, about hopper
    unsigned int rdtLen;
    unsigned char rdt[1024];
};

struct IDCErrorInfo
{
    int result;
    unsigned char rawErrorCode[4];
    unsigned char sort[128];
    unsigned char errorContents[1024];
    unsigned char errorHandle[512];
};

enum DataSource
{
    O_Source_Unk = 0,
    O_Source_Track1,
    O_Source_Track2,
    O_Source_Track3,
    O_Source_Chip,
    O_Source_Rserved,
};
struct IDCRawData
{
    DataSource source;
    int status;
    unsigned char rawData[512];
    unsigned long len;
};
enum ChipPowerType
{
    O_ChipPowerDefault = 0,
    O_ChipPowerCold,
    O_ChipPowerWarm,
    O_ChipPowerOff,
};

enum ChipProtocolType
{
    O_Chip_Unk = 0,
    O_Chip_T0,
    O_Chip_T1,
};

enum BoxStatus
{
    O_Box_Unk = 0,
    O_Box_Miss,
    O_Box_Empty,
    O_Box_Low,
    O_Box_Ok,
    O_Box_High,
    O_Box_Full,
};
struct CUStatus
{
    int BoxCount;
    BoxStatus status[8];
};
struct RetainBinStatus
{
    int BoxCount;
    BoxStatus status[8];
};

#define CWERR_IDC_BASE                    21000000
#define CWERR_IDC_S_BASE                  CWERR_IDC_BASE + 200000  // Sankyo

namespace Sankyo
{
// Sankyo error type definition
#define CWERR_IDC_S_HW_BASE                 CWERR_IDC_S_BASE + 10000
#define CWERR_IDC_S_SOFT_BASE               CWERR_IDC_S_BASE + 20000
// ...
#define CWINFO_IDC_S_INFO_BASE              CWERR_IDC_S_BASE + 90000

// Sankyo soft error definition
#define CWERR_IDC_S_SOFT_UNK                CWERR_IDC_S_SOFT_BASE + (0001)

// Positive response from CHU
#define CWINFO_IDC_S_EMPTY                  CWINFO_IDC_S_INFO_BASE + (1000)  // Sankyo: "00"
#define CWINFO_IDC_S_GATE                   CWINFO_IDC_S_INFO_BASE + (1001)  // Sankyo: "01"
#define CWINFO_IDC_S_INSIDE                 CWINFO_IDC_S_INFO_BASE + (1002)  // Sankyo: "02"

// Error
#define CWERR_IDC_S_CMD_UNDEF               CWERR_IDC_S_HW_BASE + (1000)  // Sankyo: "00"
#define CWERR_IDC_S_CMD_PARM                CWERR_IDC_S_HW_BASE + (1001)  // Sankyo: "01"
#define CWERR_IDC_S_CMD_SEQ                 CWERR_IDC_S_HW_BASE + (1002)  // Sankyo: "02"
#define CWERR_IDC_S_CMD_NO_DEV              CWERR_IDC_S_HW_BASE + (1003)  // Sankyo: "03"
#define CWERR_IDC_S_CMD_DATA                CWERR_IDC_S_HW_BASE + (1004)  // Sankyo: "04"
#define CWERR_IDC_S_CMD_LOCKED              CWERR_IDC_S_HW_BASE + (1005)  // Sankyo: "05"
#define CWERR_IDC_S_CMD_NO_KEY              CWERR_IDC_S_HW_BASE + (1006)  // Sankyo: "06"
#define CWERR_IDC_S_JAM                     CWERR_IDC_S_HW_BASE + (1010)  // Sankyo: "10"
#define CWERR_IDC_S_SHUTTER                 CWERR_IDC_S_HW_BASE + (1011)  // Sankyo: "11"
#define CWERR_IDC_S_SENSOR                  CWERR_IDC_S_HW_BASE + (1012)  // Sankyo: "12"
#define CWERR_IDC_S_LONG                    CWERR_IDC_S_HW_BASE + (1013)  // Sankyo: "13"
#define CWERR_IDC_S_SHORT                   CWERR_IDC_S_HW_BASE + (1014)  // Sankyo: "14"
#define CWERR_IDC_S_ROM                     CWERR_IDC_S_HW_BASE + (1015)  // Sankyo: "15"
#define CWERR_IDC_S_FORCE                   CWERR_IDC_S_HW_BASE + (1016)  // Sankyo: "16"
#define CWERR_IDC_S_RETRY_JAM               CWERR_IDC_S_HW_BASE + (1017)  // Sankyo: "17"
#define CWERR_IDC_S_SW_ERR                  CWERR_IDC_S_HW_BASE + (1018)  // Sankyo: "18"
#define CWERR_IDC_S_NO_R_INSERT             CWERR_IDC_S_HW_BASE + (1019)  // Sankyo: "19"
#define CWERR_IDC_S_READ_P                  CWERR_IDC_S_HW_BASE + (1020)  // Sankyo: "20"
#define CWERR_IDC_S_READ                    CWERR_IDC_S_HW_BASE + (1021)  // Sankyo: "21"
#define CWERR_IDC_S_WRITE                   CWERR_IDC_S_HW_BASE + (1022)  // Sankyo: "22"
#define CWERR_IDC_S_READ_NO_DATA            CWERR_IDC_S_HW_BASE + (1023)  // Sankyo: "23"
#define CWERR_IDC_S_READ_NO_TRACK           CWERR_IDC_S_HW_BASE + (1024)  // Sankyo: "24"
#define CWERR_IDC_S_WRITE_Q                 CWERR_IDC_S_HW_BASE + (1025)  // Sankyo: "25"
#define CWERR_IDC_S_READ_SS                 CWERR_IDC_S_HW_BASE + (1026)  // Sankyo: "26"
#define CWERR_IDC_S_READ_ES                 CWERR_IDC_S_HW_BASE + (1027)  // Sankyo: "27"
#define CWERR_IDC_S_READ_LRC                CWERR_IDC_S_HW_BASE + (1028)  // Sankyo: "28"
#define CWERR_IDC_S_WRITE_V                 CWERR_IDC_S_HW_BASE + (1029)  // Sankyo: "29"
#define CWERR_IDC_S_POWER_D                 CWERR_IDC_S_HW_BASE + (1030)  // Sankyo: "30"
#define CWERR_IDC_S_CAPTURE_FAIL            CWERR_IDC_S_HW_BASE + (1040)  // Sankyo: "40"
#define CWERR_IDC_S_IC_PRESS_FAIL           CWERR_IDC_S_HW_BASE + (1041)  // Sankyo: "41"
#define CWERR_IDC_S_IC_POS_FAIL             CWERR_IDC_S_HW_BASE + (1043)  // Sankyo: "43"
#define CWERR_IDC_S_FORCE_EJECT             CWERR_IDC_S_HW_BASE + (1045)  // Sankyo: "45"
#define CWERR_IDC_S_NO_WITHDRAWN            CWERR_IDC_S_HW_BASE + (1046)  // Sankyo: "46"
#define CWERR_IDC_S_OVER_COUNT              CWERR_IDC_S_HW_BASE + (1050)  // Sankyo: "50"
#define CWERR_IDC_S_MOTOR_ERR               CWERR_IDC_S_HW_BASE + (1051)  // Sankyo: "51"
#define CWERR_IDC_S_DECODE_ERR              CWERR_IDC_S_HW_BASE + (1053)  // Sankyo: "53"
#define CWERR_IDC_S_ANT_PIN_ERR             CWERR_IDC_S_HW_BASE + (1054)  // Sankyo: "54"
#define CWERR_IDC_S_ANT_PIN_PRESSED         CWERR_IDC_S_HW_BASE + (1055)  // Sankyo: "55"
#define CWERR_IDC_S_ANT_MOVING              CWERR_IDC_S_HW_BASE + (1058)  // Sankyo: "58"
#define CWERR_IDC_S_ICC_POWER_ERR           CWERR_IDC_S_HW_BASE + (1060)  // Sankyo: "60"
#define CWERR_IDC_S_ATR_ERR                 CWERR_IDC_S_HW_BASE + (1061)  // Sankyo: "61"
#define CWERR_IDC_S_PROTOCOL_DISAGREE       CWERR_IDC_S_HW_BASE + (1062)  // Sankyo: "62"
#define CWERR_IDC_S_IC_COM_ERR              CWERR_IDC_S_HW_BASE + (1063)  // Sankyo: "63"
#define CWERR_IDC_S_IC_OTHER_ERR            CWERR_IDC_S_HW_BASE + (1064)  // Sankyo: "64"
#define CWERR_IDC_S_IC_WAIT_ATR             CWERR_IDC_S_HW_BASE + (1065)  // Sankyo: "65"
#define CWERR_IDC_S_PROTOCOL_UNSUPPORT      CWERR_IDC_S_HW_BASE + (1066)  // Sankyo: "66"
#define CWERR_IDC_S_EMV_MULT_CARD           CWERR_IDC_S_HW_BASE + (1067)  // Sankyo: "67"
#define CWERR_IDC_S_EMV_FAIL                CWERR_IDC_S_HW_BASE + (1069)  // Sankyo: "69"
#define CWERR_IDC_S_HOP_EMPTY               CWERR_IDC_S_HW_BASE + (1100)  // Sankyo: "A0"
#define CWERR_IDC_S_CARD_LEAD               CWERR_IDC_S_HW_BASE + (1101)  // Sankyo: "A1"
#define CWERR_IDC_S_MST_TIME_OVER           CWERR_IDC_S_HW_BASE + (1102)  // Sankyo: "A2"
#define CWERR_IDC_S_MST_RETRY               CWERR_IDC_S_HW_BASE + (1103)  // Sankyo: "A3"
#define CWERR_IDC_S_MST_RETRY1              CWERR_IDC_S_HW_BASE + (1104)  // Sankyo: "A4"
#define CWERR_IDC_S_HOP_JAM                 CWERR_IDC_S_HW_BASE + (1105)  // Sankyo: "A5"
#define CWERR_IDC_S_HOP_POS                 CWERR_IDC_S_HW_BASE + (1106)  // Sankyo: "A6"
#define CWERR_IDC_S_MST_MOTOR               CWERR_IDC_S_HW_BASE + (1107)  // Sankyo: "A7"
#define CWERR_IDC_S_MST_SENSOR              CWERR_IDC_S_HW_BASE + (1108)  // Sankyo: "A8"
#define CWERR_IDC_S_SLIDER_EMPTY            CWERR_IDC_S_HW_BASE + (1109)  // Sankyo: "A9"
#define CWERR_IDC_S_REJECT_ABNORMAL         CWERR_IDC_S_HW_BASE + (1110)  // Sankyo: "AB"
#define CWERR_IDC_S_NEED_INIT               CWERR_IDC_S_HW_BASE + (1111)  // Sankyo: "B0"
#define CWERR_IDC_S_UNKNOWN                 CWERR_IDC_S_HW_BASE + (9999)

//metal detector error defination
#define CWERR_IDC_METALDETECTOROPENERR		(CWERR_IDC_S_HW_BASE + 2001)		// 异物探测装置打开失败
#define CWERR_IDC_METALDETECTEDERROR                    (CWERR_IDC_S_HW_BASE + 2002)		// 异物探测装置探测到异物

}

/*   restore alignment   */
#pragma pack(pop)

#endif //SANKYODEF